1. Field of the Invention
This invention relates to integrated circuit fabrication, and more particularly, to a semiconductor device having a self-aligned metal-containing gate structure and to a method for producing this device.
2. Description of the Relevant Art
The formation of self-aligned source and drain regions is a well-established technique in MOSFET fabrication. These source and drain regions exhibit minimal overlap with the transistor gate, minimizing the parasitic capacitances that limit high-frequency transistor performance. In general, the self-alignment is achieved by fabricating a gate conductor, and subsequently using the gate conductor as a mask for implantation of dopant impurities to form the source and drain. Because it is formed before the implantation and subsequent annealing of the source and drain impurities, the gate conductor must be made from a material which can withstand high-temperature processing.
The current material of choice for gate conductors in MOSFET fabrication is polycrystalline silicon, or polysilicon. Although polysilicon has good high-temperature properties, it has high resistivity compared to that of a metal. The resistance R of a material region can be defined in terms of the material's resistivity, p, the region's cross-sectional area, A, and the region's length, l, using the equation R=pl/A. As features on integrated circuits become smaller, area A decreases, and it becomes more and more important for resistivity to be low in order to achieve low resistances. The resistivity of a polysilicon gate conductor is typically lowered by doping. The doping is often performed by ion implantation, using the same implants which dope the self-aligned source and drain. Problems arise with this process, however, because typical gate conductor thicknesses are greater than the depths of the shallow junctions required for source and drain regions in high-performance devices. In order to achieve relatively shallow junctions, the lower portion of the polysilicon gate conductor receives fewer dopants than the upper portion. The region of the gate conductor adjacent to the gate dielectric therefore has a higher resistivity, and the resulting device performs as if it had an increased gate dielectric thickness. If the implantation depth is increased to more completely dope the gate conductor profile, however, the source and drain regions may extend too far into the substrate.
A gate conductor made from a low-resistance metal would alleviate many of the problems with polysilicon gate conductors discussed above. Unfortunately, low-resistance metals such as aluminum are not able to withstand the high-temperature processing needed, for example, to anneal the as-implanted source and drain regions employed within a standard self-aligned process. It would therefore be desirable to develop a method of forming self-aligned gates using low-resistance metals or metal alloys.